1. Field of the Invention
The present invention relates to a solid-state imaging device and an electronic instrument, such as camera, equipped with the solid-state imaging device.
2. Description of the Related Art
Among known solid-state imaging devices (or image sensors) are CCD (Charge Coupled Device) solid-state imaging devices and CMOS (Complementary Metal Oxide Semiconductor) solid-state imaging devices. They are used for digital still cameras, digital video cameras, and various portable terminal equipment such as portable telephone with a built-in camera.
The generally-known CCD solid-state imaging device has photoelectric conversion elements (photodiodes) arranged in an array and also has between their rows the vertical transfer parts of CCD structure which read out the charges resulting from photoelectric conversion. It additionally has the horizontal transfer part of CCD structure, which transfers the signal charges sent from the vertical transfer parts, and the output part, which converts the signal charges sent from the horizontal transfer part into voltage and then sends it out. The CCD solid-state imaging device mentioned above has the vertical transfer part, the horizontal transfer part, and the output part covered with a light-shielding film of metallic material such as tungsten. And the light-shielding film has openings formed on the photoelectric conversion elements individually.
Among the known CMOS solid-state imaging devices is the solid-state imaging device which, owing to its global shutter function, transfers the signal charges (resulting from photoelectric conversion by the photoelectric conversion element or the photodiode) all at once to the charge holding part. Like the CCD solid-state imaging device, the solid-state imaging device with the global shutter function also has the light-shielding film of tantalum or tungsten that covers its surface except for the photodiodes and contact openings.
There are new CCD solid-state imaging devices under development which permit the light-shielding film to function as an electrode for reduction of dark current. An example of such CCD solid-state imaging devices is shown in FIG. 17, cited from Patent Document 1. It includes of the n-type semiconductor substrate 301, the p-type well region 302, and the n-type semiconductor region (or photodiode) 303 for photoelectric conversion, which are sequentially formed one over another. The photoelectric conversion region 303 has the accumulation region 329 of high concentration p-type, which is formed on the surface thereof. The p-type well region 302 has the p-type read-out region 305, the n-type transfer channel region 304, and the p-type channel stop region 306, which are formed therein. The n-type transfer channel region 304 has the p-type well region 308, which is formed immediately thereunder.
On the n-type transfer channel region 304, the p-type read-out region 305, and the p-type channel stop region 306 is formed the transfer electrode 311, with the gate insulating film interposed between them. On the transfer electrode 311 are formed the interlayer insulating film 314, with the conductive light shielding film 315 interposed between them, and the transparent conductive film 321. At the top are sequentially formed the planarizing film 318, the color filter layer 319, and the on-chip microlens 320.
The CCD solid-state imaging device (shown in FIG. 17) according to Japanese Patent No. 4247235 which is hereinafter referred to as Patent Document 1 has the conductive light shielding film 315 and the transparent conductive film 321, which are formed on the photoelectric conversion region 303, with the interlayer insulting film 314 interposed between them. These components constitute the MOS (Metal Oxide Semiconductor) capacitor structure. This structure causes the accumulation region 329 of high concentration p-type to be formed on the surface of the photoelectric conversion region 303 by application of minus voltage to the conductive light shielding film 315 and the transparent conductive film 321. The p-type accumulation region 329 formed by voltage application traps the dark current that occurs on the substrate surface in the photoelectric conversion region 303. The application of minus voltage to the conductive light shielding film 315 from voltage application means causes the signal charges to be read out to the n-type transfer channel 304 of the vertical transfer part. This step involves application of a voltage of 0 V or opposite polarity of minus polarity to the conductive light shielding film 315 from the voltage application means.
In the case of the CMOS solid-state imaging device, the floating diffusion part (FD part for short hereinafter) needs a holding time of several microseconds in normal operation or a holding time longer than the frame rate if the global shutter is to work. This poses a serious problem with the reduction of dark current in the FD part as in the case of photodiode. Unfortunately, the reduction of dark current in the FD part is not achieved effectively by the solid-state imaging device constructed as mentioned above.
An example of CMOS solid-state imaging devices is shown in FIG. 18, cited from Japanese Patent Laid-open No. 2005-142503 which is hereinafter referred to as Patent Document 2. The illustrated CMOS solid-state imaging device includes the n-type semiconductor substrate 2201, the p-type well region 2202 formed thereon, and the isolation dielectric region 2204 of LOCOS oxide film formed thereon. It also has the p-type channel stop layer 2203 in contact with the lower surface of the isolation dielectric region 2202. The p-type well region 2202 has the floating diffusion region 2205 (FD region for short hereinafter) of n-type diffusion layer formed therein, so that the photodiode (not shown) is formed and the pixel transistor is also formed which has the gate electrode 2206 formed with the gate insulation film 2207 placed thereunder.
The CMOS solid-state imaging device shown in FIG. 18 easily suffers from dark current because it has the gate electrode 2206 immediately above the depletion layer that occurs under the isolation dielectric region 2204 of LOCOS oxide film. In other words, that part where the FD region 2205 (which is a layer of n+ in high concentration) and the channel stop layer 2203 (which is a layer of p+) are close to each other is in such a state during signal reading that the FD region 2205 is given a voltage which is positive with respect to the p-type well region 2202. This implies that the pn junction is given a voltage in the reverse direction.
Moreover, FIG. 18 shows the region “b” in which the gate electrode 2206 of n+ polysilicon is formed with the isolation dielectric region 2204 placed thereunder. This gate electrode 2206 differs in work function from the p-type channel stop layer 2203 and hence the channel stop layer 2203 has its majority carrier substantially concentrated into p+ in proportion to the difference in work function even though the gate electrode 2206 is at the same potential as the p-type well region 2202. As the result, the depletion region 2208 between the FD region 2205 and the p-type well region 2202 becomes uneven such that the region “b” is shorter than the region “c” in which the gate electrode 2206 does not exist, as expressed by d1<d2. At the same time, a high electric field is applied across the FD region 2205 of n+ and the channel stop layer 2203 of p+ and this easily causes leakage current to occur. In other words, leakage current easily occurs if the material (electrode) placed near the depletion region is the one which substantially concentrates the majority carrier in the semiconductor region of opposite conduction type that forms the depletion layer by junction with the FD region.
To be more specific, leakage current easily occurs if the FD region is made of n-type silicon or aluminum which has such a work function as to substantially increase the concentration of the majority carrier in the hole region. Leakage current also easily occurs if the FD region is made of p-type silicon which has such a work function as to substantially increase the concentration of the majority carrier in the n region. In this case, therefore, it is desirable to make layout such that the depletion layer of the FD region comes least close to the p+ channel stop layer, as shown in FIG. 18.
Another example of CMOS solid-state imaging devices is shown in FIG. 19, cited from Japanese Patent Laid-open No. 2001-28433 which is hereinafter referred to as Patent Document 3. The CMOS solid-state imaging device shown in FIG. 19A includes the n-type semiconductor substrate 411, the p-type well region 412 formed thereon, the isolation dielectric region 413 of LOCOS oxide film formed thereon, the photodiode 414 of n-type semiconductor region, and the transistor 421 for read-out. The read-out transistor 421 leads the signal charge of the photodiode 414 to the vertical signal line. Moreover, it has the photodiode 414 and the n-type semiconductor region 415 as its source and drain, respectively, and also has the gate electrode 417 with the gate insulating film 416 placed thereunder. The p-type well region 412 has the p-type semiconductor region 422 therein which is so formed as to surround the isolation dielectric region 413.